Skip to content

C74-6502 CPU

A Homemade TTL 6502

  • Overview
    • Overview
    • Why build a 6502?
    • The Build Process
    • VIC-tory!
    • When I’m 64 …
  • Datasheet
  • Internals (Updated)
    • Block Diagram
    • Card A – Registers (New)
    • Card B – ALU & CU (New)
      • ALU
        • ALU Inputs
        • Logical Unit
        • The Adder
        • The Shifter
        • C.MX Decoder
        • ALU Operations
        • ALU Control Circuitry
        • BCD Adjust Logic
        • C.OUT Generation
      • P Register & Flags
        • Flag Evaluation Logic
        • P Register
        • SF.MX Decoder
        • Branch Test
      • Control Unit
        • Microcode ROMs
        • NX.MX Decoder
        • State Register (Q)
        • Microcode Pipeline
        • BRANCH.OP Detector
        • Branch Not Taken
        • BRANCH.EXIT
        • MIR.SW
        • 1BOP Detector
        • NOP1 Detector
        • INC.DPH
        • FETCH.OP
        • Inhibit INC16
        • Interrupts
          • RESET Interrupt
          • NMI Interrupt
          • IRQ Interrupt
    • Microcode (New)
    • Optimizations (Updated)
  • About The C74 Project
  • Q & A
  • Contact
  • Twitter
  • Facebook
  • Google Plus
  • Github
  • WordPress.com

The C74-6502 At Large

The C74-6502 made an appearance at World of Commodore 2018, (see show reports on c64os.com  and vintageisthenewold.com).

Below is a talk about the CPU from the conference. (Click on the image to view the video).

AA0FD72E-9593-4A3E-85C5-811CA8159291

See also the C74-6502 featured on Hackaday:

984DEDDF-1EF0-49B0-B4B0-07220F67D4B5

Posted on December 5, 2017September 11, 2020Author c74project

Post navigation

Previous Previous post: 100MHz Next Gen TTL 6502
Next Next post: The Need for Speed
Create a website or blog at WordPress.com
Cancel

 
Loading Comments...
Comment
    ×