Follow the progress of a new Next Generation TTL 6502 targeting a 100MHz clock-rate!
An often repeated refrain is that homebuilt CPUs are constrained to single-digit clock-rates by limitations inherent in discrete-component design. But we know that’s not true. The C74-6502 achieved a 20MHz clock-rate while still being a full-fledged cycle-accurate 6502. It’s worth asking, then, could a humble TTL 6502 reach that rarified air above 100MHz? It’s not clear such a thing is possible, but the challenge is on!
6502 Advanced Pipeline Design
See here a discussion of an advanced pipeline design for a 6502. This type of architecture is commonly used on RISC CPUs (like ARM) but is not often seen in older ones like the 6502. This design includes a 7-stage instruction pipeline that aims to maximize concurrency within the CPU and thereby to reduce the average number of cycles per instruction (CPI) on execution.
The discussion includes overviews of several advanced CPU design techniques, as these apply specifically to the 6502. These include:
- Data, Address and Instruction Caches
- 7-Stage Instruction Pipeline
- Branch Target Buffer
- Data and Operand Forwarding
- Branch Prediction
C74-6502 CPU 